The present invention relates to integrated circuit (IC) designs, and more particularly to a stagger memory cell array.
Advance of semiconductor technology creates new challenges for IC designs. Ideally, it is desired to have an IC design that contains a high density of electronic components, while providing a good product yield rate. However, these two objectives are often difficult to achieve at the same time. For example, there are often certain design rules for an IC designer to arrange memory cells for a static random access memory (SRAM). These design rules determine not only the dimensions of the structural components of a memory cell, but also the geographical relations among the cells. Due to the constraints of the design rules, it is often difficult to reduce the size of a memory cell array. These design rules also limit the potential for the memory cell arrays to increase its yield rate.
Thus, what is needed is a scheme that allows IC designers to increase the size or yield rate of IC devices within the constraints of design rules.